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Pipeline And Vector Processing In Computer Architecture Pdf Download, cancer cure with baking soda pdf download
084f2db8c6 This allows the value to be produced to be used at an earlier stage in the pipeline than would otherwise be possible Software Technique Instruction Scheduling(compiler) for delayed load Data hazard can be dealt with either hardware techniques or software technique Instruction Pipeline Docsity.com FORWARDING HARDWARE Register file Result write bus Bypass path ALU result buffer MUX ALU R4 MUX Instruction Pipeline Example: ADD R1, R2, R3 SUB R4, R1, R5 3-stage Pipeline I: Instruction Fetch A: Decode, Read Registers, ALU Operations E: Write the result to the destination register I A E ADD SUB I A E Without Bypassing I A E SUB With Bypassing Docsity.com INSTRUCTION SCHEDULING a = b + c; d = e - f; Unscheduled code: Delayed Load A load requiring that the following instruction not use its result Scheduled Code: LW Rb, b LW Rc, c LW Re, e ADD Ra, Rb, Rc LW Rf, f SW a, Ra SUB Rd, Re, Rf SW d, Rd LW Rb, b LW Rc, c ADD Ra, Rb, Rc SW a, Ra LW Re, e LW Rf, f SUB Rd, Re, Rf SW d, Rd Instruction Pipeline Docsity.com CONTROL HAZARDS Branch Instructions - Branch target address is not known until the branch instruction is completed - Stall -> waste of cycle times FI DA FO EX FI DA FO EX Branch Instruction Next Instruction Target address available Dealing with Control Hazards * Prefetch Target Instruction * Branch Target Buffer * Loop Buffer * Branch Prediction * Delayed Branch Instruction Pipeline Docsity.com CONTROL HAZARDS Instruction Pipeline Prefetch Target Instruction Fetch instructions in both streams, branch not taken and branch taken Both are saved until branch branch is executed. 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Ai * Bi + Ci for i = 1, 2, 3, . , 7 Ai R1 R2 Multiplier R3 R4 Adder R5 Memory Pipelining Bi Ci Segment 1 Segment 2 Segment 3 Docsity.com OPERATIONS IN EACH PIPELINE STAGE Clock Pulse Segment 1 Segment 2 Segment 3 Number R1 R2 R3 R4 R5 1 A1 B1 2 A2 B2 A1 * B1 C1 3 A3 B3 A2 * B2 C2 A1 * B1 + C1 4 A4 B4 A3 * B3 C3 A2 * B2 + C2 5 A5 B5 A4 * B4 C4 A3 * B3 + C3 6 A6 B6 A5 * B5 C5 A4 * B4 + C4 7 A7 B7 A6 * B6 C6 A5 * B5 + C5 8 A7 * B7 C7 A6 * B6 + C6 9 A7 * B7 + C7 Pipelining Docsity.com GENERAL PIPELINE General Structure of a 4-Segment Pipeline S R 1 1 S R 2 2 S R 3 3 S R 4 4 Input Clock Space-Time Diagram 1 2 3 4 5 6 7 8 9 T1 T1 T1 T1 T2 T2 T2 T2 T3 T3 T3 T3 T4 T4 T4 T4 T5 T5 T5 T5 T6 T6 T6 T6 Clock cycles Segment 1 2 3 4 Pipelining Docsity.com PIPELINE SPEEDUP n: Number of tasks to be performed Conventional Machine (Non-Pipelined) tn: Clock cycle t1: Time required to complete the n tasks t1 = n * tn Pipelined Machine (k stages) tp: Clock cycle (time to complete each suboperation) tk: Time required to complete the n tasks tk = (k + n - 1) * tp Speedup Sk: Speedup Sk = n*tn / (k + n - 1)*tp n Sk = tn tp ( = k, if tn = k * tp ) lim Pipelining Docsity.com PIPELINE AND MULTIPLE FUNCTION UNITS P1 I i P2 I i+1 P3 I i+2 P4 I i+3 Multiple Functional Units Example - 4-stage pipeline - subopertion in each stage; tp = 20nS - 100 tasks to be executed - 1 task in non-pipelined system; 20*4 = 80nS Pipelined System (k + n - 1)*tp = (4 + 99) * 20 = 2060nS Non-Pipelined System n*k*tp = 100 * 80 = 8000nS Speedup Sk = 8000 / 2060 = 3.88 4-Stage Pipeline is basically identical to the system with 4 identical function units Pipelining Docsity.com ARITHMETIC PIPELINE Floating-point adder  Compare the exponents  Align the mantissa  Add/sub the mantissa  Normalize the result X = A x 2a Y = B x 2b R Compare exponents by subtraction a b R Choose exponent Exponents R A B Align mantissa Mantissas Difference R Add or subtract mantissas R Normalize result R R Adjust exponent R Segment 1: Segment 2: Segment 3: Segment 4: Arithmetic Pipeline Docsity.com 4-STAGE FLOATING POINT ADDER A = a x 2 p B = b x 2 q p a q b Exponent subtractor Fraction selector Fraction with min(p,q) Right shifter Other fraction t = p - q r = max(p,q) Fraction adder Leading zero counter r c Left shifter c Exponent adder r s d d Stages: S1 S2 S3 S4 C = A + B = c x 2 = d x 2 r s (r = max (p,q), 0.5 d 4-Stage Pipeline  FI: Fetch an instruction from memory  DA: Decode the instruction and calculate the effective address of the operand  FO: Fetch the operand  EX: Execute the operation Instruction Pipeline Docsity.com INSTRUCTION PIPELINE Execution of Three Instructions in a 4-Stage Pipeline Instruction Pipeline FI DA FO EX FI DA FO EX FI DA FO EX i i+1 i+2 Conventional Pipelined FI DA FO EX FI DA FO EX FI DA FO EX i i+1 i+2 Docsity.com INSTRUCTION EXECUTION IN A 4-STAGE PIPELINE 1 2 3 4 5 6 7 8 9 10 12 13 11 FI DA FO EX 1 FI DA FO EX FI DA FO EX FI DA FO EX FI DA FO EX FI DA FO EX FI DA FO EX 2 3 4 5 6 7 FI Step: Instruction (Branch) Instruction Pipeline Fetch instruction from memory Decode instruction and calculate effective address Branch? Fetch operand from memory Execute instruction Interrupt? Interrupt handling Update PC Empty pipe no yes yes no Segment1: Segment2: Segment3: Segment4: Docsity.com MAJOR HAZARDS IN PIPELINED EXECUTION Structural hazards(Resource Conflicts) Hardware Resources required by the instructions in simultaneous overlapped execution cannot be met Data hazards (Data Dependency Conflicts) An instruction scheduled to be executed in the pipeline requires the result of a previous instruction, which is not yet available JMP ID PC + PC bubble IF ID OF OE OS Branch address dependency Hazards in pipelines may make it necessary to stall the pipeline Pipeline Interlock: Detect Hazards Stall until it is cleared Instruction Pipeline ADD DA B,C + INC DA +1 R1 bubble Data dependency R1 Two-port memory will serve without stall Instruction Pipeline FI DA FO EX i i+1 i+2 FI DA FO EX FI DA FO EX stall stall Docsity.com DATA HAZARDS Data Hazards Occurs when the execution of an instruction depends on the results of a previous instruction ADD R1, R2, R3 SUB R4, R1, R5 Hardware Technique Interlock - hardware detects the data dependencies and delays the scheduling of the dependent instruction by stalling enough clock cycles Forwarding (bypassing, short-circuiting) - Accomplished by a data path that routes a value from a source (usually an ALU) to a user, bypassing a designated register.